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true bipolar input, dual 1 s, 12-/14-bit, 2-channel sar adcs ad7366/ad7367 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features dual 12-bit/14-bit, 2-channel adc true bipolar analog inputs programmable input ranges: 10 v, 5 v, 0 v to 10 v 12 v with 3 v external reference throughput rate: 1 msps simultaneous conversion with read in less than 1s high analog input impedance low current consumption: 8.3 ma typical in normal mode 320na typical in shutdown mode ad7366 72 db snr at 50 khz input frequency 12-bit no missing codes ad7367 76 db snr at 50 khz input frequency 14-bit no missing codes accurate on-chip reference: 2.5 v 0.2% C40c to +85c operation high speed serial interface spi-/qspi?-/microwire?-/dsp-compatible i cmos ? process technology available in a 24-lead tssop functional block diagram 12-/14-bit successive approximation adc d out a output drivers control logic t/h buf v a1 v a2 mux ref ad7366/ad7367 v drive d cap a a v cc dv cc buf d out b output drivers 12-/14-bit successive approximation adc t/h v b1 v b2 agnd agnd v ss dgnd d cap b cs sclk cnvst busy addr range0 range1 refsel mux v dd 06703-001 figure 1. general description the ad7366/ad7367 1 are dual, 12/14-bit, high speed, low power, successive approximation analog-to-digital converters (adcs) that feature throughput rates up to 1 msps. the device contains two adcs, each preceded by a 2-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier. the ad7366/ad7367 are fabricated on the analog devices, inc. industrial cmos process ( i cmos? 2 ), which is a technology platform combining the advantages of low and high voltage cmos. the process allows the ad7366/ad7367 to accept high voltage bipolar signals in addition to reducing power consump- tion and package size. the ad7366/ad7367 can accept true bipolar analog input signals in the 10 v range, 5 v range, and 0 v to 10 v range. the ad7366/ad7367 have an on-chip 2.5 v reference that can be disabled to allow the use of an external reference. if a 3 v reference is applied to the d cap a and d cap b pins, the ad7366/ad7367 can accept a true bipolar 12 v analog input. minimum 12 v v dd and v ss supplies are required for the 12 v input range. product highlights 1. the ad7366/ad7367 can accept true bipolar analog input signals, as well as 10 v, 5 v, 12 v (with external refer- ence), and 0 v to +10 v unipolar signals. 2. two complete adc functions allow simultaneous sampling and conversion of two channels. 3. 1 msps serial interface; spi-/qspi-/dsp-/microwire- compatible interface. table 1. related products device resolution throughput rate number of channels ad7366 12-bit 1 msps dual, 2-channel ad7366-5 12-bit 500 ksps dual, 2-channel ad7367 14-bit 1 msps dual, 2-channel ad7367-5 14-bit 500 ksps dual, 2-channel 1 protected by u.s. patent no. 6,731,232. 2 icmos process technology. for an alog systems designers within industrial/instrumentation equipment oems who need high performance ics at higher voltage levels, i cmos is a technology platform that enables the development of analog ic s capable of 30 v and oper ating at 15 v supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.
ad7366/ad7367 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 11 terminology .................................................................................... 14 theory of operation ...................................................................... 16 circuit information.................................................................... 16 converter operation.................................................................. 16 analog inputs.............................................................................. 16 transfer function ....................................................................... 17 typical connection diagram ................................................... 18 driver amplifier choice ........................................................... 19 reference ..................................................................................... 19 modes of operation ....................................................................... 20 normal mode.............................................................................. 20 shutdown mode ......................................................................... 21 power-up times......................................................................... 21 serial interface ................................................................................ 22 microprocessor interfacing........................................................... 24 ad7366/ad7367 to adsp-218x.............................................. 24 ad7366/ad7367 to adsp-bf53x........................................... 24 ad7366/ad7367 to tms320vc5506..................................... 25 ad7366/ad7367 to dsp563xx................................................ 25 application hints ........................................................................... 27 layout and grounding .............................................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 5/07revision 0: initial version
ad7366/ad7367 rev. 0 | page 3 of 28 specifications t a = ?40c to +85c, av cc = dv cc = 4.75 v to 5.25 v, v dd = 11.5 v to 16.5 v, v ss = ?16.5 v to ?11.5 v, v drive = 2.7 v to 5.25 v, f sample = 1.12 msps, f sclk = 48 mhz, v ref = 2.5 v internal/external, t a = t min to t max , unless otherwise noted. table 2. ad7366 parameter min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise ratio (snr) 1 70 72 db signal-to-noise + distortion ratio (sinad) 1 70 71 db total harmonic distortion (thd) 1 ?85 ?78 db spurious-free dynamic range (sfdr) 1 ?87 ?78 db intermodulation distortion (imd) 1 fa = 49 khz, fb = 51 khz second-order terms ?88 db third-order terms ?88 db channel-to-channel isolation 1 ?90 db sample and hold aperture delay 2 10 ns aperture jitter 2 40 ps aperture delay matching 2 100 ps full power bandwidth 35 mhz @ 3 db, 10 v range 8 mhz @ 0.1 db, 10 v range dc accuracy resolution 12 bits integral nonlinearity (inl) 1 0.5 1 lsb differential nonlinearity (dnl) 1 0.25 0.5 lsb guaranteed no missed codes to 12 bits positive full-scale error 1 1 7 lsb 5 v and 10 v analog input range 1 6 lsb 0 v to 10 v analog input range positive full-scale error match 1 1.5 lsb matching from adc a to adc b 0.1 lsb channel to channel matching for adc a and adc b zero code error 1 0.5 3 lsb 5 v and 10 v analog input range 1 6 lsb 0 v to 10 v analog input range zero code error match 1 1.5 lsb matching from adc a to adc b 0.1 lsb channel-to-channel matching for adc a and adc b negative full-scale error 1 1 7 lsb 5 v and 10 v analog input range 1 6 lsb 0 v to 10 v analog input range negative full-scale error match 1 1.5 lsb matching from adc a to adc b 0.1 lsb channel-to-channel matching for adc a and adc b analog input input voltage ranges 10 v (programmed via range pins) 5 v 0 to 10 v dc leakage current 0.01 1 a input capacitance 9 pf when in track, 10 v range 13 pf when in track, 5 v or 0 v to 10 v range input impedance 260 k for 10 v @1 msps 2.5 m for 10 v @100 ksps 125 k for 5 v/ 0 v to 10 v @1 msps 1.2 m for 5 v/ 0 v to 10 v @100 ksps
ad7366/ad7367 rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments reference input/output reference output voltage 3 2.495 2.5 2.505 v 0.2% max @ 25c long-term stability 150 ppm for 1000 hours output voltage hysteresis 1 50 ppm reference input voltage range 2.5 3.0 v dc leakage current 0.01 1 a external reference applied to pin d cap a/pin d cap b input capacitance 25 pf 5 v and 10 v analog input range 17 pf 0 v to 10 v analog input range d cap a, d cap b output impedance 7 reference temperature coefficient 6 25 ppm/c v ref noise 20 v rms bandwidth = 3 khz logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.01 +0.8 v input current, i in 1 a v in = 0 v or v drive input capacitance, c in 2 6 pf logic outputs output high voltage, v oh v drive ? 0.2 v output low voltage, v ol 0.4 v floating state leakage current 0.01 1 a floating state output capacitance 2 8 pf conversion rate conversion time 610 ns track/hold acquisition time 2 140 ns full-scale step input throughput rate 1.12 msps for 4.75 v v drive 5.25 v, f sclk = 48 mhz 1 msps for 2.7 v v drive < 4.75 v, f sclk = 35 mhz power requirements digital inputs = 0 v or v drive v cc 4.75 5.25 v see table 7 v dd +11.5 +16.5 v see table 7 v ss ?16.5 ?11.5 v see table 7 v drive 2.7 5.25 v normal mode (static) i dd 370 550 a v dd = +16.5 v i ss 40 60 a v ss = ?16.5 v i cc 1.5 1.8 ma v cc = 5.5 v normal mode (operational) f s = 1.12 msps i dd 1.8 2.0 ma v dd = +16.5 v i ss 1.5 1.6 ma v ss = ?16.5 v i cc 5 5.6 ma v cc = 5.25 v, internal reference enabled shutdown mode i dd 0.01 1 a v dd = +16.5 v i ss 0.01 1 a v ss = ?16.5 v i cc 0.3 2 a v cc = 5.25 v power dissipation normal mode (operational) 88.8 mw v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v, f s = 1.12 msps 50 mw 10 v input range, f s = 1.12 msps, 70 mw 5 v and 0 v to 10 v input range, f s = 1.12 msps shutdown mode 1.9 43.5 w v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v 1 see the terminology section. 2 sample tested during initial release to ensure compliance. 3 refers to pin d cap a or pin d cap b specified for 25 o c.
ad7366/ad7367 rev. 0 | page 5 of 28 t a = ?40c to +85c, av cc = dv cc = 4.75 v to 5.25 v, v dd = 11.5 v to 16.5 v, v ss = ?16.5 v to ?11.5 v, v drive = 2.7 v to 5.25 v, f sample = 1 msps, f sclk = 48 mhz, v ref = 2.5 v internal/external, t a = t min to t max , unless otherwise noted. table 3. ad7367 parameter min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise ratio (snr) 1 74 76 db signal-to-noise + distortion ratio (sinad) 1 73 75 db total harmonic distortion (thd) 1 ?84 ?78 db spurious-free dynamic range (sfdr) 1 ?87 ?79 db intermodulation distortion (imd) 1 fa = 49 khz, fb = 51 khz second-order terms ?91 db third-order terms ?89 db channel-to-channel isolation 1 ?90 db sample and hold aperture delay 2 10 ns aperture jitter 2 40 ps aperture delay matching 2 100 ps full power bandwidth 35 mhz @ 3 db, 10 v range 8 mhz @ 0.1 db, 10 v range dc accuracy resolution 14 bits integral nonlinearity (inl) 1 2 3.5 lsb differential nonlinearity (dnl) 1 0.5 0.90 lsb guaranteed no missed codes to 14 bits positive full-scale error 1 4 20 lsb 5 v and 10 v analog input range 5 20 lsb 0 v to 10 v analog input range positive full-scale error match 1 3 lsb matching from adc a to adc b 0.2 lsb channel to channel matching for adc a and adc b zero code error 1 1 10 lsb 5 v and 10 v analog input range 5 20 lsb 0 v to 10 v analog input range zero code error match 1 3 lsb matching from adc a to adc b 0.2 lsb channel to channel matching for adc a and adc b negative full-scale error 1 4 20 lsb 5 v and 10 v analog input range 5 20 lsb 0 v to 10 v analog input range negative full-scale error match 1 3 lsb matching from adc a to adc b 0.2 lsb channel-to-channel matching for adc a and adc b analog input input voltage ranges 10 v (programmed via range pins) 5 v 0 to 10 v see table 7 dc leakage current 0.01 1 a input capacitance 9 pf when in track, 10 v range 13 pf when in track, 5 v or 0 v to 10 v range input impedance 260 k for 10 v @ 1 msps 2.5 m for 10 v @ 100 ksps 125 k for 5 v/0 v to 10 v @ 1 msps 1.2 m for 5 v/0 v to 10 v @ 100 ksps
ad7366/ad7367 rev. 0 | page 6 of 28 parameter min typ max unit test conditions/comments reference input/output reference output voltage 3 2.495 2.5 2.505 v 0.2% max @ 25c long-term stability 150 ppm for 1000 hours output voltage hysteresis 1 50 ppm reference input voltage range 2.5 3.0 v dc leakage current 0.01 1 a external reference applied to d cap a/pin d cap b input capacitance 25 pf 5 v and 10 v analog input range 17 pf 0 v to 10 v analog input range d cap a, d cap b output impedance 7 reference temperature coefficient 6 25 ppm/c v ref noise 20 v rms bandwidth = 3 khz logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.8 v input current, i in 0.01 1 a v in = 0 v or v drive input capacitance, c in 2 6 pf logic outputs output high voltage, v oh v drive ? 0.2 v output low voltage, v ol 0.4 v floating state leakage current 0.01 1 a floating state output capacitance 2 8 pf conversion rate conversion time 680 ns track/hold acquisition time 2 140 ns full-scale step input; throughput rate 1 msps for 4.75 v v drive 5.25 v, f sclk = 48 mhz 900 ksps for 2.7 v v drive < 4.75 v, f sclk = 35 mhz power requirements digital inputs = 0 v or v drive v cc 4.75 5.25 v see table 7 v dd +11.5 +16.5 v see table 7 v ss ?16.5 ?11.5 v see table 7 v drive 2.7 5.25 v normal mode (static) i dd 370 550 a v dd = +16.5 v i ss 40 60 a v ss = ?16.5 v i cc 1.5 1.8 ma v cc = 5.5 v normal mode (operational) f s = 1 msps i dd 1.8 2.0 ma v dd = +16.5 v i ss 1.5 1.6 ma v ss = ?16.5 v i cc 5 5.6 ma v cc = 5.25 v, internal reference enabled shutdown mode i dd 0.01 1 a v dd = +16.5 v i ss 0.01 1 a v ss = ?16.5 v i cc 0.3 2 a v cc = 5.25 v power dissipation normal mode (operational) 80.7 88.8 mw v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v 50 mw 10 v input range, f s = 1 msps 70 mw 5 v and 0 v to 10 v input range, f s = 1 msps shutdown mode 1.9 43.5 w v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v 1 see the terminology section. 2 sample tested during initial release to ensure compliance. 3 refers to pin d cap a or pin d cap b .
ad7366/ad7367 rev. 0 | page 7 of 28 timing specifications av cc = dv cc = 4.75 v to 5.25 v, v dd = 11.5 v to 16.5 v, v ss = ?16.5 v to ?11.5 v, v drive = 2.7 v to 5.25 v, t a = t min to t max , unless otherwise noted. 1 table 4. limit at t min , t max parameter 2.7 v v drive < 4.75 v 4.75 v v drive 5.25 v unit test conditions/comments t convert conversion time, internal clock. convst falling edge to busy falling edge 680 680 ns max for the ad7367 610 610 ns max for the ad7366 f sclk 10 10 khz min frequency of serial read clock 35 48 mhz max t quiet 30 30 ns min minimum quiet time required between the end of serial read and the start of the next conversion t 1 10 10 ns min minimum convst low pulse t 2 40 40 ns min convst falling edge to busy rising edge t 3 0 0 ns min busy falling edge to msb valid once cs is low for t 4 prior to busy going low t 4 10 10 ns max delay from cs falling edge until pin 1 (d out a) and pin 23 (d out b) are three-state disabled t 5 2 20 14 ns max data access time after sclk falling edge t 6 7 7 ns min sclk to data valid hold time t 7 0.3 t sclk 0.3 t sclk ns min sclk low pulse width t 8 0.3 t sclk 0.3 t sclk ns min sclk high pulse width t 9 10 10 ns max cs rising edge to d out a, d out b, high impedance t power-up 70 70 s power up time from shutdown mode; time required between convst rising edge and convst falling edge 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. all timing specifications given are with a 25 pf load capacitance. with a load capacitance greater than this value, a digital b uffer or latch must be used. see the terminology section and figure 25. 2 the time required for the output to cross is 0.4 v or 2.4 v.
ad7366/ad7367 rev. 0 | page 8 of 28 absolute maximum ratings table 5. parameter rating v dd to agnd, dgnd ?0.3 v to +16.5 v v ss to agnd, dgnd ?16.5 v to +0.3 v v drive to dgnd ?0.3 v to dv cc v dd to av cc (v cc ? 0.3 v) to +16.5 v av cc to agnd, dgnd ?0.3 v to +7 v dv cc to av cc ?0.3 v to +0.3 v dv cc to dgnd ?0.3 v to +7 v v drive to agnd ?0.3 v to dv cc agnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd v ss ? 0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to v drive + 0.3 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v d cap b, d cap b input to agnd ?0.3 v to a v cc + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 128c/w jc thermal impedance 42c/w pb-free temperature, soldering reflow 260(+0)c esd 1.5 kv 1 transient currents of up to 100 ma will not cause latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7366/ad7367 rev. 0 | page 9 of 28 pin configuration and function descriptions d out a 1 2 3 addr 4 dgnd 24 23 busy 22 cnvst 21 range0 5 range1 6 agnd 7 sclk 20 cs 19 refsel 18 8 agnd 17 9 16 10 15 11 14 12 13 ad7366/ ad7367 top view (not to scale) d out b d cap ad cap b dv cc av cc v ss v a1 v a2 v b1 v b2 v dd v drive 06703-002 figure 2. pin configuration table 6. pin function descriptions pin no. mnemonic description 1, 23 d out a, d out b serial data outputs. the data output is supplied to each pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input and 12 sclk cycles are required to access the data from the ad7366 while 14 sclk cycle are required for the ad7367. the data simultan eously appears on both pins from the simultaneous conversions of both adcs. the data stream consists of the 12 bits of conversion data for the ad7366 and 14 bits for the ad7367 and is provided msb first. if cs is held low for a further 12 sclk cycles for the ad7366 or 14 sclk cycles for the ad7367, on either d out a or d out b, the data from the other adc follows on that d out pin. this allows data from a simultaneous conversion on both ad cs to be gathered in serial format on either d out a or d out b using only one serial port. see the serial interface section for more information. 2 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. this pin should be decoupled to dgnd. the voltage range on this pin is 2.7 v to 5.25 v and may be different to the voltage at av cc and dv cc , but should never exceed either by more than 0.3 v. to achieve a throughput rate of 1.12 msps for the ad7366 or 1 msps for the ad7367, v drive must be greater than or equal to 4.75 v. 3 dv cc digital supply voltage, 4.75 v to 5.25 v. the dv cc and av cc voltages should ideally be at the same potential. for best performance, it is recommended that the dv cc and av cc pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 v even on a transient basis. this supply should be decoupled to dgnd. place 10 f and 100 nf decoupling capacitors on the dv cc pin. 4, 5 range1, range0 analog input range selection, logic inputs. the polarity on these pins determines the input range of the analog input channels. see the analog inputs section and table 8 for details. 6 addr multiplexer select, logic input. this input is used to sele ct the pair of channels to be simultaneously converted, either channel 1 of both adc a and adc b, or channel 2 of both adc a and adcb. the logic state on this pin is latched on the rising edge of busy to set up the multiplexer for the next conversion. 7, 17 agnd analog ground. ground reference point for all analog circuitry on the ad7366/ad7367. all analog input signals and any external reference signal should be referred to this agnd voltage. both agnd pins should connect to the agnd plane of a system. the agnd and dgnd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 8 av cc analog supply voltage, 4.75 v to 5.25 v. this is the supply voltage for the adc cores. the av cc and dv cc voltages should ideally be at the same potential. for best performance, it is recommended that the dv cc and av cc pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 v even on a transient basis. this supply should be decoupled to agnd. pl ace 10 f and 100 nf decoupling capacitors on the av cc pin. 9, 16 d cap a, d cap b decoupling capacitor pins. decoupling capacitors are conn ected to these pins to decouple the reference buffer for each respective adc. for best performance, it is recommended to use a 680 nf decoupling capacitor on these pins. provided the output is buffered, the on-chi p reference can be taken from these pins and applied externally to the rest of a system. 10 v ss negative power supply voltage. this is the negative su pply voltage for the high voltage analog input structure of the ad7366/ad7367. the supply must be less than a maximum voltage of ?11.5 v for all input ranges. see table 7 for further details. place 10 f and 100 nf decoupling capacitors on the v ss pin. 11, 12 v a1 , v a2 analog inputs of adc a. these are both single-ended analog inputs. the analog inp ut range on these channels is determined by the range0 and range1 pins. 13, 14 v b2 , v b1 analog inputs of adc b. these are both single-ended an alog inputs. the analog inp ut range on these channels is determined by the range0 and range1 pins. 15 v dd positive power supply voltage. this is the positive su pply voltage for the high voltage analog input structure ad7366/ad7367. the supply must be greater than a minimu m voltage of 11.5 v for all the analog input ranges. see table 7 for further details. place 10 f and 100 nf decoupling capacitors on the v dd pin.
ad7366/ad7367 rev. 0 | page 10 of 28 pin no. mnemonic description 18 refsel internal/external reference selection, logic input. if this pin is tied to logic high, the on-chip 2.5 v reference is used as the reference source for both adc a and adc b. in addition, pin d cap a and pin d cap b must be tied to decoupling capacitors. if the refsel pin is tied to gnd, an external reference can be supplied to the ad7366/ ad7367 through the d cap a and/or d cap b pins. 19 cs chip select, active low logic input. this in put frames the serial data transfer. when cs is logic low, the output bus is enabled and the conversion result is output on d out a and d out b. 20 sclk serial clock, logic input. a serial clock input pr ovides the sclk for accessing the data from the ad7366/ad7367. 21 cnvst conversion start; logic input. this pin is edge triggered. on the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated. if cnvst is low at the end of a conversion, the part goes into power-down mode. in this case, the rising edge of cnvst instructs the part to power up again. 22 busy busy output. busy transitions high when a conversion is started and remains high until the conversion is complete. 24 dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7366/ad7367. the dgnd pin should connect to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0. 3 v apart, even on a transient basis.
ad7366/ad7367 rev. 0 | page 11 of 28 typical performance characteristics t a = 25c, unless otherwise noted. 16000 14000 12000 10000 8000 6000 4000 2000 0 dnl error (lsb) code av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps t a = 25c internal reference ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 06703-003 figure 3. ad7367 typical dnl 16000 14000 12000 10000 8000 6000 4000 2000 0 inl error (lsb) code av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps t a = 25c internal reference ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 06703-004 figure 4. ad7367 typical inl ?20 0 ?40 ?60 ?80 ?100 ?120 ?140 ?160 (db) frequency (khz) 50000 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 06703-005 av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps, f in = 50khz internal reference snr = 76db, sinad = 73db figure 5. ad7367 fft ?76 ?78 ?80 ?86 ?84 ?82 10 100 1000 thd (db) analog input frequency (khz) 10v range 5v range 0v to 10v range 06703-006 av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference figure 6. thd vs. analog input frequency ?66 ?81 ?76 ?71 ?86 10 100 1000 thd (db) analog input frequency (khz) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 5v range r in = 5100 ? r in = 3000 ? r in = 3900 ? r in = 470 ? r in = 2000 ? r in = 1300 ? r in = 240 ? r in = 56 ? 06703-007 figure 7. thd vs. analog input frequency for various source impedances 77 69 71 73 75 67 10 100 1000 sinad (db) analog input frequency (khz) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 10v range 06703-008 0v to 10v range 5v range figure 8. sinad vs. analog input frequency
ad7366/ad7367 rev. 0 | page 12 of 28 ? 70 ?85 ?80 ?75 ?90 ?95 ?100 ?105 ?110 0 100 200 300 400 500 600 channel-to-channel isolation (db) frequency of input noise (khz) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 0v to 10v range 5v range 10v range 06703-009 figure 9. channel- to-channel isolation 31 codes 344 codes 8191 8192 8193 8196 8195 8194 code 06703-010 0 10000 20000 30000 40000 50000 60000 70000 80000 90000 100000 110000 106091 codes figure 10. histogram of codes for 200k samples ? 70 ?80 ?90 ?100 ?110 ?120 0 200 400 1200 1000 800 600 psrr (db) supply ripple frequency (khz) v cc , adc a v dd, adc b v dd , adc a v cc , adc b 100mv p-p sine wave on av cc no decoupling capacitor v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps v ss , adc a 06703-011 v ss , adc b figure 11. psrr vs. supply ripple frequency without supply decoupling 80 60 40 20 0 ?20 ?40 100 200 300 400 500 600 700 800 900 1000 analog input current (a) throughput rate (ksps) v in = 0v to 10v v in = +5v v in = +10v v in = ?5v v in = ?10v av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 06703-012 figure 12. analog input current vs. throughput rate
ad7366/ad7367 rev. 0 | page 13 of 28 2.5050 2.5025 2.5030 2.5035 2.5040 2.5045 2.5020 2.5015 2.5010 2.5005 2.5000 0 102030405060708090 v ref (v) current load (a) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v, 06703-013 figure 13. v ref vs. reference output current drive 0.250 0.300 0.200 0.150 0.100 0.50 0 0 500 1000 1500 2000 2500 v out or v cc ? v out (v) current (a) 06703-014 sink current source current av cc = 5v, dv cc = 5v v dd = 15v, v ss = 15v v drive = 3v, f s = 1msps internal reference figure 14. d out source current vs. (v cc ? v out ) and d out sink current vs. v out power (mv) sampling frequency (ksps) 100 400300200 600500 700 800 900 1000 15 25 35 45 55 65 av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 0v to 10v range 5v range 10v range 0 6703-017 figure 15. power vs. sampling frequency in normal mode
ad7366/ad7367 rev. 0 | page 14 of 28 terminology differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a single (1) lsb point below the first code transition and full scale, a point 1 lsb above the last code transition. zero code error it is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, that is, agnd C ? lsb for bipolar ranges and 2 v ref ? 1 lsb for the unipolar range. positive full-scale error it is the deviation of the last code transition (011110) to (011111) from the ideal (that is, +4 v ref ? 1 lsb or +2 v ref C 1 lsb) after the zero code error has been adjusted out. negative full-scale error this is the deviation of the first code transition (10000) to (10001) from the ideal (that is, ?4 v ref + 1 lsb, ?2 v ref + 1 lsb, or agnd + 1 lsb) after the zero code error has been adjusted out. zero code error match this is the difference in zero code error across all 12 channels. positive full-scale error match the difference in positive full-scale error across all channels. negative full-scale error match the difference in negative full-scale error across all channels. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of a conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ? lsb, after the end of conversion. signal-to-noise (+ distortion) ratio (sinad) this ratio is the measured ratio of signal-to-noise (+ distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process: the more levels, the smaller the quantization noise. the theoretical signal-to-noise (+ distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to-noise (+ distortion) = (6.02n + 1.76) db thus, for a 12-bit converter, this is 74 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7366/ad7367, it is defined as: 1 2 6 2 5 2 4 2 3 2 2 log20)( v vvvvv dbthd ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum. however, for adcs where the harmonics are buried in the noise floor, it is a noise peak. channel-to-channel isolation channel-to-channel isolation is a measure of the level of cross- talk between any two channels when operating in any of the input ranges. it is measured by applying a full-scale, 150 khz sine wave signal to all unselected input channels and determin- ing how much that signal is attenuated in the selected channel with a 50 khz signal. the figure given is the typical across all four channels for the ad7366/ad7367 (see the typical performance characteristics section for more information). intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion prod- ucts at the sum, and different frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the ad7366/ad7367 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually dis- tanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.
ad7366/ad7367 rev. 0 | page 15 of 28 power supply rejection ration (psrr) variations in power supply affect the full-scale transition but not the converters linearity. psrr is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see figure 11 ). thermal hysteresis thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ = +25c to t max to +25c or t_hys? = +25c to t min to +25c it is expressed in ppm using the following equation: 6 10 )25( )_()25( )( ? = cv hystvcv ppmv ref ref ref hys where: v ref (25c) is v ref at 25c. v ref (t_hys) is the maximum change of v ref at t_hys+ or t_hys?.
ad7366/ad7367 rev. 0 | page 16 of 28 theory of operation circuit information the ad7366/ad7367 are fast, dual, 2-channel, 12-/14-bit, bipolar input, simultaneous sampling, serial adcs. the ad7366/ad7367 can accept bipolar input ranges of 10 v and 5 v. it can also accept a 0 v to 10 v unipolar input range. the ad7366/ad7367 requires v dd and v ss dual supplies for the high voltage analog input structure. these supplies must be equal to or greater than 11.5 v. see table 7 for the minimum requirements on these supplies for each analog input range. the ad7366/ad7367 require a low voltage of 4.75 v to 5.25 v v cc supply to power the adc core. table 7. reference and supply requirements for each analog input range selected analog input range (v) reference voltage (v) full-scale input range (v) av cc (v) minimum v dd /v ss (v) 2.5 10 5 11.5 10 3.0 12 5 12 2.5 5 5 11.5 5 3.0 6 5 11.5 2.5 0 to 10 5 11.5 0 to 10 3.0 0 to 12 5 12 the ad7366/ad7367 contain two on-chip, track-and-hold amplifiers, two successive approximation adcs, and a serial interface with two separate data output pins. it is housed in a 24-lead tssop, offering the user considerable space-saving advantages over alternative solutions. the ad7366/ad7367 require a cnvst signal to start conversion. on the falling edge of cnvst both track-and-holds are placed into hold mode and the conversions are initiated. the busy signal goes high to indicate that the conversions are taking place. the clock source for each successive approximation adc is provided by an internal oscillator. the busy signal goes low to indicate the end of conversion. on the falling edge of busy, the track-and-hold returns to track mode. once the conversion is finished, the serial clock input accesses data from the part. the ad7366/ad7367 have an on-chip 2.5 v reference that can be disabled when an external reference is preferred. if the internal reference is to be used elsewhere in a system, then the output from d cap a and d cap b must first be buffered. on power-up, the refsel pin must be tied to either a high or low logic state to select either the internal or external reference option. if the internal reference is the preferred option, the user must tie the refsel pin logic high. alternatively, if refsel is tied to gnd then an external reference can be supplied to both adcs through d cap a and d cap b pins. the analog inputs are configured as two single-ended inputs for each adc. the various different input voltage ranges can be selected by programming the range bits as shown in table 8 . converter operation the ad7366/ad7367 have two successive approximation adcs, each based around two capacitive dacs. figure 16 and figure 17 show simplified schematics of an adc in acquisition and conversion phases. the adc is comprised of control logic, a sar, and a capacitive dac. in figure 16 (the acquisition phase), sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the signal on the input. v in agnd a b sw1 sw2 comparator capacitive dac control logic 0 6703-018 figure 16. adc acquisition phase when the adc starts a conversion (see figure 17 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the charge redis- tribution dac is used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is balanced again, the conversion is complete. the control logic generates the adc output code. v in agnd a b sw1 sw2 comparator capacitive dac control logic 0 6703-019 figure 17. adc conversion phase analog inputs each adc in the ad7366/ad7367 has two single-ended analog inputs. figure 18 shows the equivalent circuit of the analog input structure of the ad7366/ad7367. the two diodes provide esd protection. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward-biased and starts conducting current into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 170 . capacitor c1 can primarily be attributed to pin capacitance while capacitor c2 is the sampling capacitor of the adc. the total lumped capacitance of c1 and c2 is approximately 9 pf for the 10 v input range and approxi- mately 13 pf for all other input ranges.
ad7366/ad7367 rev. 0 | page 17 of 28 d d v dd c2 r1 v in 0 v ss c1 0 6703-020 figure 18. equivalent analog input structure the ad7366/ad7367 can handle true bipolar input voltages. the analog input can be set to one of three ranges: 10 v, 5 v, or 0 v to 10 v. the logic levels on pin range0 and pin range1 determine which input range is selected as outlined in table 8 . these range bits should not be changed during the acquisition time prior to a conversion, but can change at any other time. table 8. analog input range selection range1 range0 range selected 0 0 10 v 0 1 5 v 1 0 0 v to 10 v 1 1 do not program the ad7366/ad7367 require v dd and v ss dual supplies for the high voltage analog input structures. these supplies must be equal to or greater than 11.5 v. see table 7 for the require- ments on these supplies. the ad7366/ad7367 require a low voltage 4.75 v to 5.25 v av cc supply to power the adc core, a 4.75 v to 5.25 v dv cc supply for digital power, and a 2.7 v to 5.25 v v drive supply for interface power. channel selection is made via the addr pin as shown in table 9 . the logic level on the addr pin is latched on the rising edge of the busy signal for the next conversion, not the one in progress. when power is first supplied to the ad7366/ad7367 the default channel selection is v a1 and v b1 . table 9. channel selection addr channels selected 0 v a1 , v b1 1 v a2 , v b2 transfer function the output coding of the ad7366/ad7367 is twos complement. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, and so on). the lsb size is dependent on the analog input range selected. the ideal transfer charac- teristic is shown in figure 19 . table 10. lsb sizes for each analog input range ad7366 ad7367 input range full-scale range lsb size (mv) full-scale range lsb size (mv) 10 v 20 v/4096 4.88 20 v/16384 1.22 5 v 10 v/4096 2.44 10 v/16384 0.61 0 v to 10 v 10 v/4096 2.44 10 v/16384 0.61 +fsr/2 ? 1lsb analog input 0v adc code 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 ?fsr/2 + 1lsb 06703-021 figure 19. transfer characteristic track-and-hold the track-and-hold on the analog input of the ad7366/ad7367 allows the adc to accurately convert an input sine wave of full- scale amplitude to 12-/14-bit accuracy. the input bandwidth of the track-and-hold is greater than the nyquist rate of the adc. the ad7366/ad7367 can handle frequencies up to 35 mhz. the track-and-hold enters its tracking mode once the busy signal goes low after the cs falling edge. the time required to acquire an input signal depends on how quickly the sampling capacitor is charged. with zero source impedance, 140 ns is suffi- cient to acquire the signal to the 12-bit for the ad7366 and the 14-bit level for the ad7367. the acquisition time for the 10 v, 5 v, and 0 v to +10 v ranges to settle to within ? lsb is typically 140 ns. the adc goes back into hold mode on the falling edge of cnvst . the acquisition time required is calculated using the following formula: t acq = 10 (( r source + r ) c ) where: c is the sampling capacitance. r is the resistance seen by the track-and-hold amplifier looking at the input. r source should include any extra source impedance on the analog input.
ad7366/ad7367 rev. 0 | page 18 of 28 unlike other bipolar adcs, the ad7366/ad7367 do not have a resistive analog input structure. on the ad73667/ad7366, the bipolar analog signal is sampled directly onto the sampling capacitor. this gives the ad7366/ad7367 high analog input impedance. the analog input impedance can be calculated from the following formula: z = 1/(f s c s ) where: f s is the sampling frequency. c s is the sampling capacitor value. c s depends on the analog input range chosen (see the analog inputs section). when operating at 1 msps, the analog input impedance is typically 260 k for the 10 v range. as the sampling frequency is reduced, the analog input impedance further increases. as the analog input impedance increases, the current required to drive the analog input therefore decreases (see figure 7 for more information). typical connection diagram figure 20 shows a typical connection diagram for the ad7366/ ad7367. in this configuration, the agnd pin is connected to the analog ground plane of the system, and the dgnd pin is connected to the digital ground plane of the system. the analog inputs on the ad7366/ad7367 accept bipolar single- ended signals. the ad7366/ad7367 can operate with either an internal or an external reference. in figure 20 , the ad7366/ ad7367 is configured to operate with the internal 2.5 v reference. a 680 nf decoupling capacitor is required when operating with the internal reference. the av dd and dv dd pins are connected to a 5 v supply voltage. the v dd and v ss are the dual supplies for the high voltage analog input structures. the voltage on these pins must be equal to or greater than 11.5 v (see tabl e 8 for more information). the v drive pin is connected to the supply voltage of the micro- processor. the voltage applied to the v drive input controls the voltage of the serial interface. v drive can be set to 3 v or 5 v. ad7366/ ad7367 microcontroller/ microprocessor cs v drive 10f 0.1f ++ +3v or +5v supply +11.5v to +16.5 v supply ?16.5v to ?11.5v supply +5v supply dv cc av cc busy cnvst refsel v drive d cap a d cap b addr analog inputs 10v, 5v, and 0v to +10v 680nf 680nf sclk d out a d out b dgnd agnd v ss v b1 v b2 v a1 v dd v a2 10f 0.1f + + 0.1f + 10f + 0.1f + serial interface 10f + 0.1f + + + 06703-022 figure 20. typical connection diagram using internal reference
ad7366/ad7367 rev. 0 | page 19 of 28 driver amplifier choice the ad7366/ad7367 have a total of four analog inputs, which operate in single-ended mode. both adcs analog inputs can be programmed to one of the three analog input ranges. in applications where the signal source is high impedance, it is recommended to buffer the signal before applying it to the adc analog inputs. figure 21 shows the configuration of the ad7366/ad7367 in single-ended mode. in applications where the thd and snr are critical specifi- cations, the analog input of the ad7366/ad7367 should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and can necessitate the use of an input buffer amplifier. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated in the application. the thd increases as the source impedance increases and performance degrades. figure 7 shows thd vs. the analog input frequency for various source impedances. depending on the input range and analog input configuration selected, the ad7366/ad7367 can handle source impedances as illustrated in figure 7 . due to the programmable nature of the analog inputs on the ad7366/ad7367, the choice of op amp used to drive the inputs is a function of the particular application and depends on the analog input voltage ranges selected. the driver amplifier must be able to settle for a full-scale step to a 14-bit level, 0.0061%, in less than the specified acquisition time of the ad7366/ad7367. an op amp such as the ad8021 meets this requirement when operating in single-ended mode. the ad8021 needs an external compensating npo type of capacitor. the ad8022 can also be used in high frequency applications where a dual version is required. for lower fre- quency applications, recommended op amps are the ad797 , ad845 , and ad8610 . v + v? v dd v ss v a1 v cc +5v agnd ad8021 1k? 1k? 15pf c comp = 10pf ?10v/?5v +10v/+5v ad7366/ ad7367* *additional pins omitted for clarity. 10f + 0.1f + 0.1f + + 10f + 06703-023 figure 21. typical connection diagram with the ad8021 for driving the analog input v drive the ad7366/ad7367 also have a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7366/ad7367 was operated with a v cc of 5 v, the v drive pin could be powered from a 3 v supply, allow- ing a large dynamic range with low voltage digital processors. thus, the ad7366/ad7367 could be used with the 10 v input range while still being able to interface to 3 v digital parts. to achieve the maximum throughput rate of 1.12 msps for the ad7366 or 1 msps for the ad7367, v drive must be greater than or equal to 4.75 v, see table 2 and table 3 . the maximum throughput rate with the v drive voltage set to less than 4.75 v and greater than 2.7 v is 1 msps for the ad7366 and 900 ksps for the ad7367. reference the ad7366/ad7367 can operate with either the internal 2.5 v on-chip reference or an externally applied reference. the logic state of the refsel pin determines whether the internal refer- ence is used. the internal reference is selected for both adc when the refsel pin is tied to logic high. if the refsel pin is tied to gnd then an external reference can be supplied through the d cap a and d cap b pins. on power-up, the refsel pin must be tied to either a low or high logic state for the part to operate. suitable reference sources for the ad7366/ad7367 include ad780 , ad1582 , adr431 , ref193 , and adr391 . the internal reference circuitry consists of a 2.5 v band gap reference and a reference buffer. when operating the ad7366/ ad7367 in internal reference mode, the 2.5 v internal reference is available at the d cap a and d cap b pins, which should be decoupled to agnd using a 680 nf capacitor. it is recom- mended that the internal reference be buffered before applying it elsewhere in the system. the internal reference is capable of sourcing up to 150 a with an analog input range of 10 v and 70 a for both the 5 v and 0 v to 10 v ranges. if the internal reference operation is required for the adc con- version, the refsel pin must be tied to logic high on power- up. the reference buffer requires 70 s to power up and charge the 680 nf decoupling capacitor during the power-up time. the ad7366/ad7367 is specified for a 2.5 v to 3 v reference range. when a 3 v reference is selected, the ranges are 12 v, 6 v, and 0 v to +12 v. for these ranges, the v dd and v ss supply must be equal to or greater than the +12 v and ?12 v respectively.
ad7366/ad7367 rev. 0 | page 20 of 28 modes of operation the mode of operation of the ad7366/ad7367 is selected by the (logic) state of the cnvst signal at the end of a conversion. there are two possible modes of operation: normal mode and shutdown mode. these modes of operation are designed to provide flexible power management options, which can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. normal mode normal mode is intended for applications needing fast throughput rates because the user does not have to worry about any power-up times (with the ad7366/ad7367 remaining fully powered at all times). figure 22 shows the general mode of operation of the ad7366 in normal mode, while figure 23 illustrates normal mode for the ad7367. the conversion is initiated on the falling edge of cnvst as described in the circuit information section. to ensure that the part remains fully powered up at all times, cnvst must be at logic state high prior to the busy signal going low. if cnvst is at logic state low when the busy signal goes low, the analog circuitry powers down and the part ceases converting. the busy signal remains high for the duration of the conversion. the cs pin must be brought low to bring the data bus out of three-state, subsequently 12 sclk cycles are required to read the conversion result from the ad7366 while 14 sclk cycles are required to read from the ad7367. the d out lines return to three-state when cs is brought high only. if cs is left low for a further 12 sclk cycles for the ad7366 or 14 sclk cycles for the ad7367, the result from the other on chip adc is also accessed on the same d out line, as shown in figure 27 and figure 28 (see the serial interface section). once 24 sclk cycles have elapsed for the ad7366 and 28 sclk cycles for the ad7367, the d out line returns to three- state when cs is brought high and not on the 24 th or 28 th sclk falling edge. if cs is brought high prior to this, the d out line returns to three-state at that point. thus, cs must be brought high once the read is completed, as the bus does not auto- matically return to three-state upon completion of the dual result read. once a data transfer is complete and d out a and d out b have returned to three-state, another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cnvst low again. cnvst busy sclk t 2 t 1 t 3 serial read operation cs 1 12 t convert t quiet 06703-024 figure 22. normal mode operation for the ad7366 busy sclk t 2 t 1 t 3 serial read operation cs 1 14 t convert t quiet 06703-025 cnvst figure 23. normal mode operation for the ad7367
ad7366/ad7367 rev. 0 | page 21 of 28 shutdown mode shutdown mode is intended for use in applications where slow throughput rates are required. shutdown mode is suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus, shutdown. when the ad7366/ad7367 is in full power-down, all analog circuitry is powered down. the falling edge of cnvst initiates the conversion. the busy output subsequently goes high to indicate that the conversion is in progress. once the conversion is completed, the busy output returns low. if the cnvst signal is at logic low when busy goes low then the part enters shutdown at the end of the conversion phase. while the part is in shutdown mode the digital output code from the last conversion on each adc can still be read from the d out pins. to read the d out data, cs must be brought low as described in the serial interface section. the d out pins return to three-state once cs is brought back to logic high. to exit full power-down and to power up the ad7366/ad7367, a rising edge of cnvst is required. after the required power-up time has elapsed, cnvst may be brought low again to initiate another conversion, as shown in figure 24 (see the power-up times section for power-up times associated with the ad7366/ ad7367). power-up times the ad7366/ad7367 have one power down mode, which has already been described in detail in the shutdown mode section. this section deals with the power-up time required when coming out of this mode. it should be noted that the power-up times (as explained in this section) apply with the recommended capaci- tors in place on the d cap a and d cap b pins. to power up from shutdown, cnvst must be brought high and remain high for a minimum of 70 s, as shown in figure 24 . when power supplies are first applied to the ad7366/ad7367, the adc can power up with cnvst in either the low or high logic state. before attempting a valid conversion, cnvst must be brought high and remain high for the recommended power- up time of 70 s. then cnvst can be brought low to initiate a conversion. with the ad7366/ad7367 no dummy conversion is required before valid data can be read from the d out pins. if it is intended to place the part in shutdown mode when the supplies are first applied, then the ad7366/ad7367 must be powered up and a conversion initiated. however, cnvst should remain in the logic low state and when the busy signal goes low, the part enters shutdown. once supplies are applied to the ad7366/ad7367, sufficient time must be allowed for any external reference to power up and to charge the various reference buffer decoupling capacitors to their final values. busy sclk serial read operation cs 1 12 t convert t 3 t 2 enters shutdown t power-up 06703-026 cnvst figure 24. autoshutdown mode for ad7366
ad7366/ad7367 rev. 0 | page 22 of 28 serial interface figure 25 and figure 26 show the detailed timing diagram for serial interfacing to the ad7366 and the ad7367. on the falling edge of cnvst the ad7366/ad7367 simultaneously converts the selected channels. these conversions are performed using the on-chip oscillator. after the falling edge of cnvst the busy signal goes high, indicating the conversion has started. it returns low once the conversion has been completed. the data can now be read from the d out pins. cs and sclk signals are required to transfer data from the ad7366/ad7367. the ad7366/ad7367 have two output pins corresponding to each adc. data can be read from the ad7366/ ad7367 using both d out a and d out b. alternatively, a single output pin of the users choice can be used. the sclk input signal provides the clock source for the serial interface. the cs goes low to access data from the ad7366/ad7367. the falling edge of cs takes the bus out of three-state and clocks out the msb of the conversion result. the data stream consists of 12 bits of data for the ad7366 and 14 bits of data for the ad7367, msb first. the first bit of the conversion result is valid on the first sclk falling edge after the cs falling edge. the subsequent 11-/13-bits of data for the ad7366/ad7367 respectively are clocked out on the falling edge of the sclk signal. a minimum of 12 clock pulses must be provided to ad7366 to access each conversion result, while a minimum of 14 clock pulses must be provided to ad7367 to access the conversion result. figure 25 shows how a 12 sclk read is used to access the conversion results while figure 26 illustrates the case for the ad7367 with a 14 sclk read. on the rising edge of cs , the conversion is terminated and d out a and d out b go back into three-state. if cs is not brought high, but is instead held low for a further 12 sclk cycles for the ad7366 or 14 sclk cycles for the ad7367, on either d out a or d out b, the data from the other adc follows on the d out pin. this is illustrated in figure 27 and figure 28 where the case for d out a is shown. in this case, the d out line in use goes back into three-state on the rising edge of cs . if the falling edge of sclk coincides with the falling edge of cs , then the falling edge of sclk is not acknowledged by the ad7366/ad7367, and the next falling edge of the sclk is the first registered after the falling edges of the cs . the cs pin can be brought low before the busy signal goes low indicating the end of a conversion. once cs is at a logic low state the data bus is brought out of three-state. this feature can be utilized to ensure that the msb is valid on the falling edge of busy by bring cs low a minimum of t 4 nanoseconds before the busy signal goes low. the dotted cs line in figure 22 and figure 23 illustrates this. alternatively, the cs pin can be tied to a low logic state continu- ously. now the d out pins never enter three-state and the data bus is continuously active. under these conditions, the msb of the conversion result for the ad7366/ad7367 is available on the falling edge of the busy signal. the next most significant bit is available on the first sclk falling edge after the busy signal has gone low. this mode of operation enables the user to read the msb as soon as it is made available by the converter. d out a d out b three- state three-state cs sclk 1 51 2 2 34 db10 db11 db9 db8 db2 db1 db0 t 5 t 6 t 8 t 4 t 7 t 9 06703-027 figure 25. serial interface timing diagram for the ad7366 d out a d out b three- state three-state cs sclk 1 51 4 2 34 db12 db13 db11 db10 db2 db1 db0 t 5 t 6 t 8 t 4 t 7 t 9 0 6703-028 figure 26. serial interface timing diagram for the ad7367
ad7366/ad7367 rev. 0 | page 23 of 28 cs sclk 1 5 11 d out a three- state t 5 2 34 12 t 7 t 4 three- state t 8 t 6 10 db10 b db11 b db0 a db1 a 13 24 db9 a db10 a db1 b db0 b db11 a 06703-030 figure 27. reading data from both adcs on one d out line with 24 sclks for the ad7366 cs sclk 1 5 13 d out a three- state t 5 2 34 14 t 7 t 3 three- state t 8 t 6 12 db12 b db13 b db0 a db1 a 15 28 db11 a db12 a db13 a db1 b db0 b 06703-029 figure 28. reading data from both adcs on one d out line with 28 sclks for the ad7367
ad7366/ad7367 rev. 0 | page 24 of 28 microprocessor interfacing the serial interface on the ad7366/ad7367 allows the parts to be directly connected to a range of different microprocessors. this section explains how to interface the ad7366/ad7367 with some more common microcontrollers and dsp serial interface protocols. ad7366/ad7367 to adsp-218x the adsp-218x family of dsps interfaces directly to the ad7366/ad7367 without any glue logic required. the v drive pin of the ad7366/ad7367 takes the same supply voltage as that of the adsp-218x. this allows the adc to operate at a higher supply voltage than its serial interface and therefore, the adsp-218x, if necessary. this example shows both d out a and d out b of the ad7366/ad7367 connected to both serial ports of the adsp-218x. the sport0 and sport1 control registers should be set up as shown in table 11 and table 12 . table 11. sport0 control register setup setting description tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 table 12. sport1 control register setup setting description tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) isclk = 0 external serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 the connection diagram is shown in figure 29 . the adsp-218x has the tfs0 and rfs0 of the sport0 and the rfs1 of sport1 tied together. tfs0 is set as an output, and both rfs0 and rfs1 are set as inputs. the dsp operates in alternate framing mode, and the sport control register is set up as described in table 13 and table 14 . the frame synchronization signal generated on the tfs is tied to cs . ad7366/ ad7367* sclk cs adsp-218x* *additional pins omitted for clarity. sclk0 dr0 rfs0 tfs0 d out a v drive v dd d out b dr1 rfs1 sclk1 irq busy cnvst flo 06703-031 figure 29. interfacing the ad7366/ad7367 to the adsp-218x the ad7366/ad7367 busy line provides an interrupt to the adsp-218x when the conversi on is complete. the conver- sion results can then be read from the ad7366/ad7367 using a read operation. when an interrupt is received on irq from the busy signal, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and, hence, the reading of data. ad7366/ad7367 to adsp-bf53x the adsp-bf53x family of dsps interfaces directly to the ad7366/ad7367 without any glue logic required. the avail- ability of secondary receive registers on the serial ports of the blackfin? dsps means only one serial port is necessary to read from both d out a and d out b pins simultaneously. figure 30 shows both d out a and d out b of the ad7366/ad7367 con- nected to serial port 0 of the adsp-bf53x. the sport0 receive configuration 1 register and sport0 receive configuration 2 register should be set up as outlined in table 13 and table 14 . serial device a (primary) serial device b (secondary) ad7366/ ad7367* d out a cs sclk adsp-bf53x* *additional pins omitted for clarity. dr0pri pf n rfs0 v drive v dd cnvst rclk0 rxints busy dr0sec d out b sport0 0 6703-032 figure 30. interfacing the ad736 6/ad7367 to the adsp-bf53x
ad7366/ad7367 rev. 0 | page 25 of 28 table 13. the sport0 receive configuration 1 register (sport0_rcr1) setting description rckfe = 1 sample data with falling edge of rsclk lrfs = 1 active low frame signal rfsr = 1 frame every word irfs = 1 internal rfs used rlsbit = 0 receive msb first rdtype = 00 zero fill irclk = 1 internal receive clock rspen = 1 receive enabled slen = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) tfsr = rfsr = 1 table 14. the sport0 receive configuration 2 register (sport0_rcr2) setting description rxse = 1 secondary side enabled slen = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) ad7366/ad7367 to tms320vc5506 the serial interface on the tms320vc5506 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7366/ad7367. the cs input allows easy interfacing between the tms320vc5506 and the ad7366/ad7367 without any glue logic required. the serial ports of the tms320vc5506 are set up to operate in burst mode with internal clkx0 (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control registers (spc) must be setup as shown in table 15 . table 15. serial port control register set up spc fo fsm mcm txm spc0 0 1 1 1 spc1 0 1 0 0 the connection diagram is shown in figure 31 . the v drive pin of the ad7366/ad7367 takes the same supply voltage as that of the tms320vc5506. this allows the adc to operate at a higher voltage than its serial interface and, therefore, the tms320vc5506, if necessary. fsr1 fsr0 ad7366/ ad7367* sclk tms320vc5506* *additional pins omitted for clarity. clkx0 dr1 clkr1 clkx1 d out b d out a v drive v dd cs fsx0 dr0 clkr0 intn xf cnvst busy 06703-033 figure 31. interfacing the ad7366/ad7367 to the tms320vc5506 as with the previous interfaces, conversion can be initiated from the tms320vc5506 or from an external source, and the processor is interrupted when the conversion sequence is completed. ad7366/ad7367 to dsp563xx the connection diagram in figure 32 shows how the ad7366/ ad7367 can be connected to the enhanced synchronous serial interface (essi) of the dsp563xx family of dsps from motorola. there are two on-board essis, and each is operated in synchro- nous mode (bit syn = 1 in the crb register) with internally generated word length frame sync for both tx and rx (bit fsl1 = 0 and bit fsl0 = 0 in the crb register). normal operation of the essi is selected by making mod = 0 in the crb register. set the word length to 16 by setting bit wl1 = 1 and bit wl0 = 0 in the cra register. the fsp bit in the crb register should be set to 1 so that the frame sync is negative.
ad7366/ad7367 rev. 0 | page 26 of 28 in the example shown in figure 32 , the serial clock is taken from the essi0 so the sck0 pin must be set as an output (sckd = 1) while the sck1 pin is set as an input (sckd = 0). the frame sync signal is taken from sc02 on essi0, so scd2 = 1, while on essi1, scd2 = 0; therefore, sc12 is configured as an input. the v drive pin of the ad7366/ad7367 takes the same supply voltage as that of the dsp563xx. this allows the adc to operate at a higher voltage than its serial interface and, therefore, the dsp563xx, if necessary. ad7366/ ad7367* sclk dsp563xx* *additional pins omitted for clarity. sck0 sc12 srd1 srd0 cs d out a d out b v drive v dd sc02 sck1 irq n pb n cnvst busy 06703-034 figure 32. interfacing the ad7366/ad7367 to the dsp563xx
ad7366/ad7367 rev. 0 | page 27 of 28 application hints layout and grounding the printed circuit board that houses the ad7366/ad7367 should be designed so that the analog and digital sections are confined to their own separate areas of the board. this design facilitates the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum etch technique is generally the best option. all agnd pins on the ad7366/ad7367 should be connected to the agnd plane. digital and analog ground pins should be joined in only one place. if the ad7366/ad7367 are in a system where multiple devices require an agnd and dgnd connection, the connec- tion should still be made at only one point. a star point should be established as close as possible to the ground pins on the ad7366/ad7367. good connections should be made to the power and ground planes. this can be done with a single via or multiple vias for each supply and ground pin. avoid running digital lines under the ad7366/ad7367 devices because this couples noise onto the die. however, the analog ground plane should be allowed to run under the ad7366/ ad7367 to avoid noise coupling. the power supply lines to the ad7366/ad7367 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. to avoid radiating noise to other sections of the board, com- ponents, such as clocks, with fast switching signals should be shielded with digital ground and should never be run near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces should be run at right angles to each other. a microstrip technique is the best method, but its use may not be possible with a double- sided board. in this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to agnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have a low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic and surface mount types of capacitors. these low esr, low esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
ad7366/ad7367 rev. 0 | page 28 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 33. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package description package option ad7366bruz 1 ?40c to +85c 24-lead thin shrink small outline package ru-24 ad7366bruz-rl7 1 ?40c to +85c 24-lead thin shrink small outline package ru-24 ad7366bruz-500rl7 1 ?40c to +85c 24-lead thin shrink small outline package ru-24 ad7367bruz 1 ?40c to +85c 24-lead thin shrink small outline package ru-24 ad7367bruz-500rl7 1 ?40c to +85c 24-lead thin shrink small outline package ru-24 ad7367bruz-rl7 1 ?40c to +85c 24-lead thin shrink small outline package ru-24 EVAL-AD7366CBZ evaluation board eval-ad7367cbz evaluation board eval-control brd2 control board 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06703-0-5/07(0)

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